Dr. Rajan Kumar Pandey

Designation : Associate Professor Senior
School / Centre : School of Electronics Engineering
Department : Micro & Nanoelectronics

Educational Details

Indian Institute of Technology Kanpur

Ph.D
Condensed Matter Physics
Graduated in 2006

Banaras Hindu University

M.Sc
Physics
Graduated in 1998

Puravanchal University

B.Sc
Physics, Mathematics
Graduated in 1996

Post Doctoral Experiences

2005 - 2006: Department of Chemistry, University of California, Irvine CA, USA

Research Details

Areas of Specialization
  • Electronic structure of bulk and nanoscale materials
  • Computational Physics/Material Science
  • Semiconductor Device Physics
  • Computational Micro and Nano Electronics
  • High Performance Computing.

: https://orcid.org/0000-0003-2788-2317
: https://www.scopus.com/authid/detail.uri?authorId=57212632197
: https://scholar.google.co.in/citations?hl=en&user=ApxU8ScAAAAJ
: 14
: 24

Patent Granted Details

Title Application No.
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer (2019), US Patent 10,366,897
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer (2019), US Patent 10,347,494
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer (2019), US Patent 10,319,596
Stable work function for narrow-pitch devices (2019), US Patent 10,170,576
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer (2018), US Patent 9,972,497

Books / Book Chapters Published Details

Title Publisher Published Year
“Limits of Gate Dielectrics scaling”, Shahab Siddiqui, Takashi Ando, Rajan Kumar Pandey, and Dominic Schepis (Book Chapter: In the fourth edition of Handbook of Thin Film Deposition, Elsevier Publications, 2018

Awards & Recognitions Details

  • IBM (Global) Outstanding Technical Achievement Award for multi-scale modeling of High-k-Metal Gate technology for 32/22/14 nm gate length CMOS devices - December 2013.
  • IBM India Systems and Technology Group Technical Excellence Award for development and implementation of Gate Induced Drain Leakage Model in IBM in-house TCAD simulator - July 2009.
  • IBM First Plateau Invention Achievement Award – June 2012.
  • IBM Second Plateau Invention Achievement Award – April 2015.
  • Business and Technical Leadership resource at IBM India (2011 – 2015)