Dr. Antony Xavier Glittas

Designation : Assistant Professor Senior Grade 2
School / Centre : School of Electronics Engineering
Department : Micro & Nanoelectronics

Educational Details

NIT Trichy

Ph.D
Digital VLSI
Graduated in 2016

Anna university

M.E
VLSI Design
Graduated in 2012

Anand Institute of Higher Technology

B.E
ECE
Graduated in 2009

Research Details

Areas of Specialization
  • Digital VLSI
  • VLSI for DSP
  • FFT processor
  • FPGA Implementation

: https://orcid.org/ 0000-0001-5851-5689
: https://www.scopus.com/authid/detail.uri?authorId=56341147700
: https://scholar.google.co.in/citations?user=kKgBv2cAAAAJ
: 3
: 1

Patent Published Details

Title Application No.
Data scheduling register tree for radix-2 FFT architecture, 2021, US20210255804A1 (US patent).
LOW MULTIPLIER COMPLEXITY IN-PLACE HIGHER RADIX REAL-VALUED FFT ARCHITECTURES WITH MODIFIED PROCESSING ELEMENT, 2017, 201741038399 (Indian Patent).
A DATA SCHEDULING REGISTER TREE FOR RADIX-2 FFT ARCHITECTURE, 2020, 202041007125 (Indian Patent).